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Schematic Diagram
2.1 Schematic Diagram
The schematic diagram for the EVM is attached at the end of this document.
2.2 Circuit Function
The following paragraphs describe the EVM circuits.
2.2.1
2.2.2
Input Clock
Input Data
The DAC5672/62/52 EVM default operation setting is with a single-ended
input clock sent to the DAC5672/62/52. A 3 V p-p , 1.5-V offset, 50% duty cycle
external square wave is applied to SMA connector J3. This input represents
a 50- ? load to the source. In order to preserve the specified performance of
the DAC5672/62/52 converter, the clock source should feature very low jitter.
Using a clock with a 50% duty cycle will give optimum dynamic performance.
Options are provided to operate the two DAC’s with separate clocks. Another
option allows the user to provide separate write enables when using interleave
mode. See Table 2?1 for proper board configuration.
The DAC5672/62/52 EVM can accept +3.3-V CMOS logic level data inputs
through the 34-pin headers J9 and J10 per Table 2?1 and Table 2?2. The user
can provide series dampening resistors to minimize digital ringing and
switching noise if required. The default values are 0 ? . An option is also
available to provided pulldown resistors to the input data paths. Before using
the pulldown resistors, the user must make sure the source providing the input
data can drive the load the pulldown resistors adds to the data path.
Table 2?1. Input Connector J1
J9 Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Description
Port 1 Data Bit 13 (MSB)
GND
Port 1 Data Bit 12
GND
Port 1 Data Bit 11
GND
Port 1 Data Bit 10
GND
Port 1 Data Bit 9
GND
Port 1 Data Bit 8
GND
Port 1 Data Bit 7
GND
Port 1 Data Bit 6
GND
Port 1 Data Bit 5
J9 Pin No.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Description
GND
Port 1 Data Bit 4
GND
Port 1 Data Bit 3
GND
Port 1 Data Bit 2
GND
Port 1 Data Bit 1
GND
Port 1 Data Bit 0
GND
GND
GND
GND
2-2
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